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Optimization of AICu Wiring Delay in Advanced CMOS Technology

  • A. K. Stamper (a1), V. McGahay (a2), M. Shapiro (a2), L. A. Miller (a1), X. Tian (a1), A. Bryant (a1) and L. A. Serianni (a1)...

Abstract

Fluorinated high-density plasma and plasma-enhanced CVD SiO2 inter-metal dielectrics have been evaluated for 0.50- through 0.25- μm generation CMOS. Several integration issues are discussed, including the impact of fluorine-doped SiO2 on the yield, reliability, and RC delay of 0.7 - 1.8 μm pitch back-end-of-the-line AlCu/tungsten-stud wiring.

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References

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1. Matsuda, T., Shapiro, M., and Nguyen, S., Proc. 1 st Int. Diel. VLSI Multilevel Int. Conf., Santa Clara, 1995, p22.
2. Shapiro, M., Nguyen, S., and Matsuda, T., Proc. 1st Int. Diel. VLSI Multilevel Int. Conf., Santa Clara, 1995, p 118.
3. Shannon, V. L. and Karim, M. Z., Thin Solid Films 270, 1995, p498.
4. Miller, L. A. and Stamper, A. K., Proc. VLSI Multilevel Interconnection Conference, Santa Clara, CA, June, 1995 p144.

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