The performance of tunnel FETs is investigated and the impact of device structure and dimension as well as the impact of the transistor material will be studied. For instance, using nanowires with thin diameter providing one-dimensional transport together with a wrap-gate device structure strongly improves the tunnel FET performance. In addition, the use of III-V type II heterostructures is a further performance booster. However, the use of III-V semiconductors with low density of states can be problematic if the device is not designed properly. Here we will give design guidelines and performance predictions of nanowire tunnel FETs based on non-equilibrium Greens functions formalism simulations.