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Nanoporous Silica For Low K Dielectrics

  • T. Ramos (a1), K. Rhoderick (a1), R. Roth (a1), L. Brungardt (a1), S. Wallace (a1), J. Drage (a1), J. Dunne (a1), D. Endisch (a1), R. Katsanes (a1), N. Viemes (a1) and D. M. Smith (a1)...


As integrated circuit sizes decrease below 0.25 microns, device performance will no longer improve at the same rate as for past generations because of RC interconnect delay which becomes significant as compared to the intrinsic gate delay. Parallel approaches to address this are to use a lower resistance metal (i.e., copper instead of aluminum) and to use a dielectric material with a dielectric constant significantly below that of dense silica (∼4). Recently, considerable progress has been made in development of thin films of nanoporous silica for these applications. Advantages include high thermal stability, small pore size, similarity to conventional spin-on deposition processes and spin-on glass precursors and final material (silica). The dielectric constant of nanoporous silica can be tailored between ∼1 and 3 which allows its’ implementation at multiple technology nodes in integrated circuit manufacture.

Recent development efforts have been focused on; 1) simpler and more reproducible deposition processes, 2) a more complete understanding of processing-property relationships for this material, 3) scale-up of manufacturing to yield a range of precursor products with stability for at least six months and very high purity, and 4) working with customers to integrate this material into both aluminum/gapfill and copper/damascene process flows. This paper targets several specific issues related to nanoporous silica use including water adsorption, pore size distribution control, processing at commercially viable throughputs, and obtaining thickness and dielectric uniformity across 200 mm wafers and wafer to wafer.



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14 Patents pending


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