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Microstructure Based Modelling of Stress Migration and Electromigration Induced Failure Distributions

  • P. Børgesen (a1), M. A. Korhonen (a1), D. D. Brown (a1) and C.-Y. Li (a1)

Abstract

Stress and current induced degradation of the interconnects may well define the ultimate limits on device density and total on-chip power in microelectronic circuits. The two damage mechanisms are found to be mutually interdependent in a fashion determined by the line microstructure, as well as by design features such as W-studs and refractory metal back up layers. We have developed a comprehensive model for the synergistic effects of stress migration and electromigration, taking such factors into account. The present work reviews the modelling of the statistical failure distributions, with emphasis on the temperature and current density dependencies, for the case of 'near-bamboo' sub-micron lines.

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Microstructure Based Modelling of Stress Migration and Electromigration Induced Failure Distributions

  • P. Børgesen (a1), M. A. Korhonen (a1), D. D. Brown (a1) and C.-Y. Li (a1)

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