Capacitive CMOS MEMS sensors are usually defined by anisotropic dry etching processes (RIE and DRIE). These processes can provide clean and vertical sidewall geometry. However, during the dry-etching processes, charges are added to the gate electrodes of the on-chip MOSFET’s through metal pads and micro-structures, and the voltage may be raised to the level of breaking down the gate oxide, which leads to large leakage current and fails the circuit. On another hand, the thin spring beams in capacitive CMOS MEMS accelerometers suffer from in-plane curling and out-of-plane curling caused by stress gradient. Furthermore, the stress in the layers of MEMS structure is a function of temperature. Therefore, the in-plane curling and out-of-plane curling vary with temperature, leading to varying electrode coupling area in the sensing beams. This in turn causes variation in the sensitivity and the DC offset of sensors, meaning that usually the thermal stability of CMOS MEMS capacitive accelerometers is very poor. To cope with these problems, this work develops a new wafer-level post-CMOS process for fabricating thermally stable capacitive accelerometers. The resultant MEMS structures have high aspect ratio (e.g. 2-2.5 μm gaps versus 57 μm depth) and are insensitive to residual stress as well as temperature change. Excellent thermal stability was achieved intrinsically by making the crystalline Si layer in the sensors thick. Moreover, this process totally avoids the charge damage problem during the dry-etching procedure. For demonstration, an accelerometer sensor was fabricated by using the proposed process and was integrated with an on-chip sensing circuit in commercial 0.35 μm 2P4M CMOS process. High detection sensitivity of 595 mV/g and very low thermal variation of 1.68 mg/°C were successfully achieved.