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Mechanical Stresses in Aluminum and Copper Interconnect Lines for 0.18µm Logic Technologies

Published online by Cambridge University Press:  10 February 2011

Paul R. Besser ,
Young-Chang Joo ,
Delrose Winter ,
Minh Van Ngo  and
Richard Ortega
Paul R. Besser
Affiliation:
Technology Development Group of Advanced Micro Devices, Inc. One AMD Place, Sunnyvale, CA 94088. Current address: Motorola-AMD Alliance Logic Technology, 3501 Ed Bluestein Blvd, MD K-10, Austin, TX 78721.
Young-Chang Joo
Affiliation:
Technology Development Group of Advanced Micro Devices, Inc. One AMD Place, Sunnyvale, CA 94088.
Delrose Winter
Affiliation:
#AMIA Laboratories (Advanced Materials Instruments and Analysis, Inc.) 7801 North Lamar, Suite C-73, Austin, TX 78752
Minh Van Ngo
Affiliation:
Technology Development Group of Advanced Micro Devices, Inc. One AMD Place, Sunnyvale, CA 94088.
Richard Ortega
Affiliation:
#AMIA Laboratories (Advanced Materials Instruments and Analysis, Inc.) 7801 North Lamar, Suite C-73, Austin, TX 78752
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Abstract

The mechanical stress state of conventional Al and damascene Cu lines of a 0.18 pm logic technology flow have been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The effect of high density plasma oxide deposition and the influence of low-K dielectrics on the stress state of the Al lines is described. The effect of materials properties and fabrication methodology on the stress state of damascene Cu lines is shown with measurement of mechanical stress and strain in passivated lines at room temperature and during annealing. The effect of underlayer on the damascene Cu stress state is also quantified.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 563: Symposium M – Materials Reliability in Microelectronics IX , 1999 , 189
Copyright
Copyright © Materials Research Society 1999

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