During the processing and packaging of silicon integrated circuits there are many sources of die stress. Probably the least understood and controlled is the stress introduced during the die attach and molding processes. The largest packaging stresses are due to the mismatch of the thermal expansion coefficients between the leadframe and the die,and the die and the molding material. We report results obtained by monitoring the resistance changes of implanted, p-type resistors, undergoing various heat treatments with a matrix of mold and leadframe materials.