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Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications

Published online by Cambridge University Press:  01 February 2011

Jamal Qureshi ,
Raymond Caramto ,
Stephen Olson ,
Jerry Mase ,
Toshihiro Ito  and
Eiichi Yamamoto
Jamal Qureshi
Affiliation:
jqureshi@uamail.albany.edu, SEMATECH, 3D Interconnect, Albany, New York, United States
Raymond Caramto
Affiliation:
rcaramto@uamail.albany.edu, SEMATECH, 3D Interconnect, Albany, New York, United States
Stephen Olson
Affiliation:
solson@uamail.albany.edu, SEMATECH, 3D Interconnect, Albany, New York, United States
Jerry Mase
Affiliation:
jmase@uamail.albany.edu, SEMATECH, 3D Interconnect, Albany, New York, United States
Toshihiro Ito
Affiliation:
t.ito@okamoto.co.jp, OKAMOTO Machine Tool Works, LTD., Process R&D, Annaka, Gunma, Japan
Eiichi Yamamoto
Affiliation:
e.yamamoto@okamoto.co.jp, OKAMOTO Machine Tool Works, LTD., Process R&D, Annaka, Gunma, Japan
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Abstract

3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed.

Keywords

CMPslurrybonding
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1249: Symposia E/F – Advanced Interconnects and Chemical Mechanical Planarization for Micro-and Nanoelectronics , 2010 , 1249-E01-02
Copyright
Copyright © Materials Research Society 2010

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References

1 Garrou, Philip, How Might 3-D ICs Come Together?, Semiconductor International, October 2008.Google Scholar
2 Garrou, Philip, 3-D ICs Enter Commercialization, Semiconductor International, November 2008.Google Scholar
3 Kim, Y. S. et al., Ultra Thinning 300-mm Wafer down to 7-μm for 3D Wafer Integration on 45-nm Node CMOS using Strained Silicon and Cu/Low-k Interconnects, 2009 IEEE International Electron Devices Meeting (IEDM).Google Scholar
4 Blaustein, Philip et al., Full-FieId Submicron Visual Wafer Inspection, http://www.hologenix.com/Article.htm, March 2010.Google Scholar
5 Majeed, Bivragh et al., Microstructural, mechanical, fractural and electrical characterization of thinned and singulated silicon test die, book of Micromechanics and Microengineering, Institute of Physics Publishing, 16 (2006) 1519–1529.Google Scholar
6 Murugesan, M. et al., Impact of Remnant Stress/Strain and Metal Contamination in 3D-LSIs with Through-Si Vias Fabricated by Wafer Thinning and Bonding, 2009 IEEE International Electron Devices Meeting (IEDM).Google Scholar
7 Sandireddy, Sandhya et al., Advanced Wafer thinning technologies to enable multichip packages, IEEE workshop on microelectronics and electronic devices, 2005.Google Scholar
8 Charlet, Barbara et al., Patterned wafers backside thinning for 3-D Integration and multiplayer stack achievement by direct wafer bonding, Materials Research Society, Symposium Proceedings, Volume 1079, 2008.Google Scholar
9 McLellan, Neil et al., Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die, Transactions of the ASME, Vol. 126, March 2004.Google Scholar
10 Teh, W.H. et al., “A route towards production-worthy 5 μm x 25 μm and 1 μm x 20 μm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration,” in Proc. of the IEEE International 3D System Integration (3DIC), San Francisco, USA, 2009.Google Scholar