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Low Temperature Process Technologies for the Next Generation High Performance Polycrystalline Silicon Thin-Film Transistors

  • Seiichiro Higashi (a1), Daisuke Abe (a1), Satoshi Inoue (a1) and Tatsuya Shimoda (a1)

Abstract

Low temperature process technologies for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are discussed based on the investigations of pulsed laser crystallization, plasma treatment of poly-Si films, and SiO2/Si interface formation. Although highdensity (∼1018 cm−3) trap states localized at grain boundaries are introduced to the poly-Si films by laser crystallization, they are efficiently decreased to the order of 1016 cm−3 by following hydrogen plasma treatment. It is also shown that high quality SiO2/Si interfaces with the density of interface trap states (D it ) in the order of 1010 cm−2eV−1 are achieved using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). By applying these low temperature process technologies to the fabrication process, high performance poly-Si TFTs with high n-channel mobility μ n ) of 187 cm2V−1s−1, low threshold voltage (Vth ) of 1.97 V and small subthreshold swing (S) of 210 mV/dec. were obtained. These results indicate that the development of low temperature process technologies that can control trap states is the key to the next generation high performance poly-Si TFTs.

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Low Temperature Process Technologies for the Next Generation High Performance Polycrystalline Silicon Thin-Film Transistors

  • Seiichiro Higashi (a1), Daisuke Abe (a1), Satoshi Inoue (a1) and Tatsuya Shimoda (a1)

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