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Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

Abstract

A 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

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Keywords

Localized Charge Trapping Memory Cells in a 63 nm Generation with Nanoscale Epitaxial Cobalt Salicide Buried Bitlines

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