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Laser Direct Write Technologies as Tools for Gate-Array Development* *

  • D. J. Silversmith (a1), D. J. Ehrlich (a1), J. Y. Tsao (a1), R. W. Mountain (a1) and J. H. C. Sedlacek (a1)...

Abstract

Using CMOS, poly-Si gate, single-level metal, gate-array chips, techniques have been developed to reconfigure the interconnect metallization on individual circuits without degradation of device or circuit performance. These techniques involve a laser-assisted capillary wet-etch process for highly selective removal of Al-alloy interconnects and laser CVD of doped poly-Si links. This technique may be useful for prototyping, testing and optimization of gate-array and standard-cell designs and layouts.

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*

This work was sponsored by the Defense Advanced Research Projects Agency, by the Department of the Air Force, in part under a specific program supported by the Air Force Office of Scientific Research, and by the Army Research Office.

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1. Hardage, C., “CMOS Gate Arrays: Evaluation Criteria and Design,” MIDCON/81 Conference Record, Chicago, 12 Nov. 1981;
1a Hardage, C., “The CMOS Gate Array Customer/Vendor Interface,” WESCON/82 Conference Record, Anaheim, CA, 14–16 Sept. 1982.
2. Walker, T. and Broadhurst, D., “Gate Arrays - What the Spec Sheet Won't Tell You,” Electronic Products, p. 53, February 7, 1983.
3. Eidsmore, S., “Designers Guide to Gate Arrays,” Digital Design, p. 60, May 1983.
4. Ehrlich, D. J., Tsao, J. Y., Silversmith, D. J., Sedlacek, J. H. C., Mountain, R. W. and Graber, W. S., IEEE Electron Dev. Lett. (to be published Feb. 1984).
5. Tsao, J. Y. and Ehrlich, D. J., Appl. Phys. Lett. 43, 146 (1983).
6. Ehrlich, D. J. and Tsao, J. Y., “Laser Direct Writing for VLSI,” to be published in VLSI Electronics: Microstructure Science Vol 7, Einspruch, N. G., ed. (Academic, New York);
6a Ehrlich, D. J. and Tsao, J. Y., “A Review of Laser Microchemical Processing,” J. Vac. Sci. Technol. B-l, 969 (1983).
7. McWilliams, B. M., Herman, I. P., Hyde, R. A., Mitlitsky, F. and Wood, L. L., Appl. Phys. Lett. 43, 946 (1983).

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