Hostname: page-component-8448b6f56d-xtgtn Total loading time: 0 Render date: 2024-04-24T08:54:16.740Z Has data issue: false hasContentIssue false

Ion Beam Lithography And Resist Processing for Nanofabrication

Published online by Cambridge University Press:  26 February 2011

Khalil Arshak
Affiliation:
khalil.arshak@ul.ie, University of Limerick, ECE, ECE Dept., UL, Limerick, N/A, Ireland, +35361202267, +35361338176
Stephen F. Gilmartin
Affiliation:
Stephen.Gilmartin@analog.com, Analog Devices, Wafer Fabrication, Limerick, N/A, Ireland
Damien Collins
Affiliation:
damien.collins@analog.com, Analog Devices, Wafer Fabrication, Limerick, N/A, Ireland
Olga Korostynska
Affiliation:
olga.korostynska@ul.ie, University of Limerick, ECE, ECE Dept., UL, Limerick, N/A, Ireland
Arousian Arshak
Affiliation:
arousian.arshak@ul.ie, University of Limerick, Physics, Limerick, N/A, Ireland
Miroslav Mihov
Affiliation:
miroslav.m.mihov@intel.com, Intel, Fab24, Liexlip, co. Kildare, N/A, Ireland
Get access

Abstract

The International Technology Roadmap for Semiconductors (ITRS) identifies the shrinking of lithography critical dimensions (CDs) as one of biggest challenges facing the semiconductor industry as it progresses to smaller geometry nodes. Nanolithography, the patterning of masking CDs below 100nm, enables both nanoscale wafer processing and the exploration of novel nanotechnology applications and devices.

Focused Ion Beam (FIB) lithography has significant advantages over alternative nanolithography techniques, particularly when comparing resist sensitivity, topography effects, proximity effects and backscattering. FIB lithography uses the implantation of ions, such as Ga+, in its masking process. Ions implanted into resist in this manner typically have shallow penetration depths (<100nm for Ga+), and this would typically require the use of very thin resist layers during processing. This is often incompatible with subsequent fabrication steps such as plasma etching, where thicker resist layers are usually required to facilitate etch selectivity. Top surface imaging (TSI) is a solution to this problem.

When compared with conventional microelectronic lithography, nanolithography techniques such as EUV, electron beam and nanoimprint lithography require expensive process equipment and the use of non-standard process materials.

The 2-step negative resist image by dry etching (2-step NERIME) process is a FIB TSI scheme developed for DNQ/novolak based resists, and involves FIB exposure of resist with Ga+, followed by O2 plasma dry development using reactive ion etching. The 2-step NERIME process uses equipment sets and materials commonly found in microelectronic device fabrication (FIB tool, O2 plasma etcher, DNQ/novolak resists), and provides a low-cost and convenient nanolithography option for proof-of-concept nanoscale processing.

To be of practical use, a nanolithography scheme must be capable of patterning nanoscale resist features over substrate topography while retaining resist profile control. The nanolithography scheme must also integrate with subsequent plasma etch processing steps that etch various material films such as metals, Si, SiO2, SiN. The 2-step NERIME FIB TSI process has been used to successfully pattern nanoscale (40nm-90nm) resist features on planar and topography substrates. We have also demonstrated sub-100nm etched features on topography substrates using the 2-step NERIME process, reporting 80nm Polycide and TiN etched features, and 90nm Ti etched features, that exhibit excellent profiles and minimal line edge roughness (LER).

It is expected that the 2-step NERIME FIB TSI process will be further extended to etch sub-40nm features over topography substrates. The nanoscale etched features will be used to explore proof-of-concept geometry shrink & novel structures, with many possible applications, including NEMs and nanosensors research and development.

Type
Research Article
Copyright
Copyright © Materials Research Society 2007

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Morimoto, H., Sasaki, Y., Saitoh, K., Watakabe, Y., Kato, T., Microelectron. Eng. 4, (1986) 163.Google Scholar
2. Gamo, K., Microelectron. Eng. 32, (1996) 159.Google Scholar
3. Matsui, S., Mori, K., Saigo, K., Shiokawa, T., Toyoda, K., Namba, S., J. Vac. Sci. Technol. B4 (1986) 845.Google Scholar
4. Harthey, M., Shaver, D., Shepard, M., Melngailis, J., Medvedev, V., Robinson, W., J. Vac. Sci. Technol. B9, (1991) 3432.Google Scholar
5. Herbert, P., Braddell, J., MacKenzie, S., Woodham, R., Cleaver, J., Microelectron. Eng. 23, (1994) 263.Google Scholar
6. Arshak, K., Mihov, M., Sutton, D., Arshak, A., Newcomb, S. B., Microelectron. Eng. 67, (2003) 130.Google Scholar
7. Arshak, K., Mihov, M., Arshak, A., McDonagh, D., Sutton, D., Newcomb, S., J. Vac. Sci.Technol. B22, (2004) 189.Google Scholar
8. Arshak, K., Mihov, M., Shohei, N., Arshak, A., McDonagh, D., Superlatt. & Microstruct. 36, (2004) 335.Google Scholar
9. Arshak, K., Gilmartin, S. F., Collins, D., Korostynska, O., Arshak, A., Mihov, M., Proc. NSTI Nanotech Conf., Anaheim, Cal., 8–12 May, 2005, 4 (2005) 263.Google Scholar
10. Gilmartin, S. F., Arshak, K., Collins, D., Korostynska, O., Arshak, A., Proc. 5th IEEE Conference on Nanotechnology, Nagoya, 11–15 July,2005, 709.Google Scholar
11. Gilmartin, S. F., Arshak, K., Collins, D., Korostynska, O., Arshak, A., Microelectron. Eng. 83, (2006) 823.Google Scholar
12. Gilmartin, S. F., Arshak, K., Collins, D., Korostynska, O., Arshak, A., Proc. 6th IEEE Conference on Nanotechnology, Cincinnati, 17–20 July, 2006, 709.Google Scholar