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Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology

Abstract

During the MOS transistors fabrication process, the source-drain extension areas are directly in contact with the oxide liner of the spacers stack. In previous works [1, 2, 3] it has been established that boron can diffuse from the source-drain extensions into the spacer oxide liner during the subsequent annealing steps, and that the amount of boron loss depends on the hydrogen content in the oxide, because it enhances B diffusivity in SiO2.

In order to characterize and quantify the above phenomena, we performed test experiments on full sheet samples, which mimic either BF2 source-drain extensions over arsenic pockets implants, or BF2 pockets under arsenic or phosphorus source-drain extensions implants. Following the corresponding implants, the wafers were covered with different spacer stacks (oxide + nitride) deposited either by LPCVD, or PECVD. After appropriate activation annealing steps, SIMS measurements were used to characterize the profiles of the various dopants, and the corresponding dose loss was evaluated for each species.

Our experimental results clearly evidence that LPCVD or PECVD spacer stacks have no influence on the arsenic profiles. On the other hand, phosphorus and boron profiles are affected. For boron profiles, each spacer type has a different influence. It is also shown that boron out-diffuses not only from the B doped source-drain extension in direct contact with the oxide layer, but also from the "buried" B pockets lying under n-doped source drain extension areas. All these results are discussed in term of the possible relevant mechanism.

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References

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1 Fair, R.B. - IEEE Electron Device Letters, 17 (11), 497499 (1996)
2 Chakravarthi, S., Kohli, P., Chidambaram, P.R., Bu, H., Jain, A., Hornung, B. and Machala, C.F. – IEEE Symp. Proc., pp.159162 (2003)
3 Morin, P., Wacquant, F., Juhel, M., Laviron, C., Lenoble, D., Material Science and Engineering B, 124–125, pp.319322 (2005)
4 Wang, H. Chih-Hao and al – IEEE Elec. Device Let., 22 (2), pp. 65 (2001)
5 Kohli, P., Jain, A., Bu, H., Chakravarthi, S., Machala, C., Dunham, S.T. and Banerjee, S.K.J. Vac. Sci. Technol., B 22 (1), pp. 471476 (2004)
6 Aoyama, T., Suzuki, K., Tashiro, H., Toda, Y., Yamazaki, T., Tazaki, K. and Ito, T., J. Appl. Phys., 77 (1), pp.417419 (1995)
7 Boucard, F., Schott, M., Mathiot, D., Rivallin, P., Holliger, P. and Guichard, E., Mater. Res. Soc. Symp. Proc. 669, J8.3.1 (2001)

Keywords

Interaction Between Low Temperatures Spacers and Source Drain Extensions and Pockets for Both NMOS and PMOS of the 65 nm Node Technology

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