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Integration Challenges of Inorganic Low-K (K≤2.5) Materials with CU for Sub-0.25μm Multilevel Interconnects

Abstract

The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.

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Integration Challenges of Inorganic Low-K (K≤2.5) Materials with CU for Sub-0.25μm Multilevel Interconnects

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