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Improved Performance and Reliability in Aggressively-Scaled NMOS and PMOS FETs: i) Monolayer Interface Nitridation, and ii) Replacement of Stacked Oxide/Nitride Dielectrics With Optimized Oxide/Oxynitride Stacks

Published online by Cambridge University Press:  10 February 2011

Hanyang Yang ,
Hiro Niimi  and
Gerry Lucovsky
Hanyang Yang
Affiliation:
Department of Electrical and Computer Engineering Physics, North Carolina State University, Raleigh, NC 27695-8202
Hiro Niimi
Affiliation:
Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-8202
Gerry Lucovsky
Affiliation:
Department of Electrical and Computer Engineering Physics, North Carolina State University, Raleigh, NC 27695-8202 Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-8202 Department of Physics, North Carolina State University, Raleigh, NC 27695-8202
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Abstract

This paper demonstrates optimized performance and reliability in ‘second generation’ gate dielectrics which include monolayer nitrided Si-SiO2 interfaces, and deposited silicon oxynitride alloy gate dielectrics. Devices with oxynitride alloy gate dielectrics with an approximate 2:1 ratio of N:O display reduced tunneling current, improved hole mobilities and improved reliability compared to devices with Si-nitride gate dielectrics and the same nitrided interface.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 592 , 1999 , 177
Copyright
Copyright © Materials Research Society 2000

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