Skip to main content Accessibility help
×
Home

High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors

  • N. Tosic (a1), F. G. Kuper (a1) (a2) and T. Mouthaan (a1)

Abstract

In this paper, an analysis of the high voltage induced degradation in top gate amorphous silicon Thin Film Transistors (TFT) will be shown, including the aspect of self-heating. It will be shown through experimental results that the degradation level under high voltages on drain and gate is different for TFT's with different channel lengths. In addition, the temperature distribution over the TFT area for devices with different channel length is simulated. Simulation shows that the peak of temperature distribution is located at the drain/channel edge and that level of thermal heating depends on the channel length.

Copyright

References

Hide All
1. Tosic, N., Kuper, F.G., Mouthaan, T., “Transmission line model testing of top-gate amorphous silicon thin-film transistors”, Proc. of IRPS 2000 Conference.
2. Tada, M., Uchikoga, S., Ikeda, M., “Power-density-dependent failure of amorphous Si TFT”, Proc. of AM-LCD '96, pp. 269272.

High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors

  • N. Tosic (a1), F. G. Kuper (a1) (a2) and T. Mouthaan (a1)

Metrics

Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed