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Gate Technology Issues for Silicon Mos Nanotransistors

Published online by Cambridge University Press:  10 February 2011

D. M Tennant
Affiliation:
Bell Laboratories, Lucent Technologies, Holmdel,N.J. 07733
G. L. Timp
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
L. E. Ocola
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
M. Green
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
T. Sorsch
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
A. Komblit
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
F. Klemens
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
R. Kleiman
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
D. A. Muller
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
Y. Kim
Affiliation:
Bell Laboratories,Lucent Technologies, Murray Hill, N.J. 07974
W. Timp
Affiliation:
University of Illinois, Champaign-Urbana, Illinois 61820
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Abstract

This article reviews technology issues in scaling conventional planar transistors to a physical gate length of 30nm that are expected to produce an effective channel length of 10 nm. Gate fabrication features direct write e-beam lithography to form a ring structure capable of exploring the practical limits of gate processing while requiring only a single level of lithography. Other processing elements include ultra-thin gate dielectric formation (∼ 0.6nm); highly selective transformer coupled plasma (TCP) etching; and low energy ion implantation. DC electrical results obtained for high performance n-MOS and p-MOS type nanotransistors made using this process are discussed as are simulations of sub-threshold currents for n-MOS transistors with physical gate lengths down to 26nm

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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