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Ferroelectric-Gate Structures and Field-Effect Transistors Using (Bi,La)4Ti3O12 Films

  • Eisuke Tokumitsu (a1), Takuya Suzuki (a1) and Naoki Sugita (a1)

Abstract

We have fabricated and characterized metal-ferroelectric-metal-insulator-semiconductor (MFMIS) diodes and field-effect-transistors (FETs) using (Bi,La)4Ti3O12 (BLT) films. 9-nm-thick SiO2 is used as an “I” layer. It is shown that the memory window in the capacitance-voltage (C-V) characteristics of the MFMIS structures is as large as 3V for a voltage sweep of 5V, when the area ratio of the MIS region (SI) to the ferroelectric capacitor region (SF), SI/SF, is 15. It is also demonstrated that the MFMIS-FETs using Pt/BLT(150nm)/Pt/SiO2(9nm)/Si structures have hysteresis loops due to the ferroelectric BLT film in the drain current-gate voltage (ID-VG) characteristics. Observed threshold voltage shift is 3V and excellent data retention characteristics are demonstrated for the device with an area ratio SI/SF of 15.

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Ferroelectric-Gate Structures and Field-Effect Transistors Using (Bi,La)4Ti3O12 Films

  • Eisuke Tokumitsu (a1), Takuya Suzuki (a1) and Naoki Sugita (a1)

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