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Evaluating Oxide Liner and Copper Barrier Integrity of Through-Silicon-Via by Electrical Characterization and Microanalysis

  • Minrui Yu (a1), Bharat Bhushan (a2), Niranjan Kumar (a1), Mun Kyu Park (a1), John Hua (a1), Shwetha Bolagond (a1), Anthony C-T. Chan (a1), Miao Jin (a1), Yuri Uritsky (a1), Chin-hock Toh (a2), Arvind Sundarrajan (a2), John Dukovic (a1) and Sesh Ramaswami (a1)...

Abstract

3D integration enabled by through-silicon-via (TSV) allows continued performance enhancement and power reduction for semiconductor devices, even without further scaling. For TSV wafers with all Applied Materials unit processes, we evaluate the integrity of oxide liner and copper barrier by capacitance-voltage (C-V) and current-voltage (I-V) measurements, from which oxide capacitance, minimum TSV capacitance, and leakage current are extracted. The capacitance values match well with model predictions. The leakage data also demonstrate good wafer-scale uniformity. The liner and barrier quality are further verified with microanalysis techniques.

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References

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2. Li, Y., et al. ., “Electrical Characterization Method to Study Barrier Integrity in 3D Through-Silicon Vias, ” IEEE 62nd ECTC, pp. 304, San Diego, California, June 2012.
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Keywords

Evaluating Oxide Liner and Copper Barrier Integrity of Through-Silicon-Via by Electrical Characterization and Microanalysis

  • Minrui Yu (a1), Bharat Bhushan (a2), Niranjan Kumar (a1), Mun Kyu Park (a1), John Hua (a1), Shwetha Bolagond (a1), Anthony C-T. Chan (a1), Miao Jin (a1), Yuri Uritsky (a1), Chin-hock Toh (a2), Arvind Sundarrajan (a2), John Dukovic (a1) and Sesh Ramaswami (a1)...

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