In narrow metal lines used for chip level interconnects, the line width can strongly affect the electromigration reliability, typically due to variations in the microstructure and in the mechanical stress state. These variations have a stronger effect as the line width decreases to the order of the metal grain size or less. Electromigration failure distributions were obtained both experimentally and by simulation for realistic interconnect structures with six different line widths, ranging from lμm to 8μm. In order to simulate the electromigration failure distributions, microstructure statistics were obtained (using TEM) and the critical void volume for failure was measured (using SEM) for each line width. The simulated failure times match the experimental failure times for narrow line widths (1-4μm).