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Effects of Top Insulator Overlap on the Stability in Hydrogenated Amorphous Silicon Thin Film Transistors

  • H.S. Choi (a1), Y.S. Kim (a1), S.K. Lee (a1), J.K. Yoon (a1), W.S. Park (a1) and Andm. K. Han (a1)...

Abstract

The effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.

In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.

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