The nitride-based SONOS cell, for its excellent scalability and process simplicity, is the candidate to push the scaling roadmap for FLASH memories beyond the limit imposed on floating-gate memories by the electrostatic interference between adjacent cells. The traditional SONOS cell consists of a nitride layer (the storage element) encapsulated by two SiO2 layers which isolate the nitride layer from the Si substrate and the poly-Si gate (Poly-Si/SiO2/Si3N4/SiO2/c-Si). However, the thick tunnel oxide necessary to meet the retention requirements imposes a severe limit on the erase performance because of the erase saturation phenomenon. One possibility to guarantee both the erase and the retention performance is the replacement of the top SiO2 layer with materials of higher dielectric constant (high-k dielectric). The presence of a high-k dielectric reduces the electric field across the top dielectric, thus decreasing the unwanted parasitic electron injection from the gate during the erase operation. This will allow the cell to erase deep so to meet a basic requirement for Gigabit multilevel NAND memories. The introduction of high-k materials in the SONOS stack is unfortunately not straightforward. One problem is the Fermi-level pinning at the poly-Si/high-k interface. Another problem is the morphological changes the high-k material undergoes during the device fabrication thermal budget. These changes can modify the k-value and affect the band offset between gate and high-k material. The results may, in both cases, be the decrease of the barrier for electron injection from the gate and, as a consequence, the deterioration of the erase performance. In this paper we study the effect of gate material and of the morphological transformation associated with the high-k post deposition anneal on the erase and the retention behaviour of nitride-based cells. Two different high-k dielectrics are investigated: Al2O3 (which has already been found to be able to significantly improve the erase operation, guaranteeing at the same time excellent endurance and sufficient bake retention) and HfAlO. We show that both for Al2O3 and HfAlO a trade-off exists between erase and retention, higher PDA temperatures being beneficial for erase but detrimental for retention. We also discuss the effect of Fermi level pinning and poly-Si depletion on the erase behaviour and compare the erase performances of several PVD- and AVD-deposited metal gates.