Skip to main content Accessibility help

Effect of Spacer Scaling on PMOS Transistors

  • Wai Shing Lau (a1), Chee Wee Eng (a2), David Vigar (a3), Lap Chan (a4) and Soh Yun Siah (a5)...


Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.



Hide All
1 Shishiguchi, S., Mineji, A. and Matsuda, T., Jpn. J. Appl. Phys., vol. 42, pp. 72657271 (2003).
2 Ye, Q. and Biesmans, S., Solid-State Electron., vol. 48, pp. 163166 (2004).
3 Eyben, P., Duhayon, N., Stuer, C., Wolf, I. De, Rooyackers, R., Clarysse, T., Vandervorst, W. and Badenes, G., MRS Symp. Proc, vol. 669, pp. J2.2.1–J2.2.6 (2001).
4 Lundstrom, M. S., IEEE Electron Dev. Lett., vol. 18, pp. 361363 (1997).
5 Lundstrom, M. S., IEEE Electron Dev. Lett., vol. 22, pp. 293295 (2001).
6 Liao, H., Lee, P.S., Goh, L.N.L., Liu, H., Sudijono, J.L., Elgin, W. and Sanford, C., Thin Solid Films, vol. 462–463, pp. 2933 (2004).



Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed