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Effect of SiC Power DMOSFET Threshold-Voltage Instability

Published online by Cambridge University Press:  01 February 2011

Aivars Lelis
Affiliation:
alelis@arl.army.mil, U.S. Army Research Laboratory, AMSRD-ARL-SE-DP, 2800 Powder Mill Rd, Adelphi, MD, 20783, United States
D. Habersat
Affiliation:
DHabersat@arl.army.mil, U.S. Army Research Laboratory, 2800 Powder Mill Rd, Adelphi, MD, 20783, United States
R. Green
Affiliation:
rgreen@arl.army.mil, U.S. Army Research Laboratory, 2800 Powder Mill Rd, Adelphi, MD, 20783, United States
A. Ogunniyi
Affiliation:
aderinto.ogunniyi@arl.army.mil, U.S. Army Research Laboratory, 2800 Powder Mill Rd, Adelphi, MD, 20783, United States
M. Gurfinkel
Affiliation:
moshegur@post.tau.ac.il, NIST, Gaithersburg, MD, 20899, United States
J. Suehle
Affiliation:
john.suehle@nist.gov, NIST, Gaithersburg, MD, 20899, United States
N. Goldsman
Affiliation:
neil@umd.edu, University of Maryland, College Park, MD, 20742, United States
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Abstract

We have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

REFERENCES

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