For BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very important to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length = 800μ, thickness = 0.7μ, widths = 1, 5, 10 μ) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si3N4, was used as passivation. DC stress was performed at 175, 200, and 225°C. Microbeam X-ray Diffraction (μ XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.