The gate/source overlap distance (ΔLs) is an important factor in fabricating self-aligned TFT with passivating layer. Six types of TFT were fabricated using thin intrinsic a-Si layers such as 20 nm,50 nm and 100 nm and a n+:a-Si or a n+:μc-Si were used as the contact layer. The least required gate/source overlap distance, ΔLsC is the critical overlap where the TFT performance is not limited by the contact. This ΔLsc was determined experimentally. ΔLsC was found to be significantly affected by the intrinsic a-Si layer thickness and the ΔLsc can be small by depositing a thin intrinsic layer. The intrinsic layer thickness dependence of ΔLsC in the linear region can be explained from a existing model. However, the behavior in the saturation region suggests the need of another model, which will be discussed here. The variation of n'contact layer shown to have a small effect on ΔLsc. In order to determine appropriate ΔLs for self-alignment TFT, the magnitude of field effect mobility, threshold voltage and drain current as well as ΔLscmust be considered.