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Direct Growth of III-V Devices on Silicon


Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.



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1. Mazuré, Carlos and Celler, George K.. “Advanced Electronic Substrates for the Nanotechnology Era.”, The Electrochemical Society Interface, Winter (2006-2007).
2. Deguet, C., Sanchez, L., Akatsu, T., Allibert, F., Dechamp, J., Madeira, F., Mazen, F., Tauzin, A., Loup, V., Richtarch, C., Mercier, D., Signamarcheix, T., Letertre, F., Depuydt, B., and Kernevez, N.. “Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium.” Electronics Letters 42 (7) 30 March (2006): 415417.
3. Maleville, C. and Mazure, C.. “Smart CutTM technology: From 300 mm ultrathin SOI production to advanced engineered substrates.” Solid-State Electron. 48 (6) June (2004). 10551063.
4.Molecular-beam epitaxy production of large-diameter metamorphic high electron mobility transistor and heterojunction bipolar transistor wafers, by Baklenov, O., Lubyshev, D., Wu, Y., Fang, X.-M., Fastenau, J.M., Leung, L., Towner, F.J., Cornfeld, A.B., and Liu, W.K., published May/June 2002
5.Monolithic CMOS-compatible AlGaInP visible LED arrays on Silicon on Lattice-Engineered Substrates (SOLES), by Chilukuri, Kamesh, Mori, Michael J., Dohrmanand, Carl L., Fitzgerald, Eugene A., published November 2006



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