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A Dimple-Array Interconnect Technique for Power Semiconductor Devices

  • Simon S. Wen (a1), Daniel Huff (a2) and Guo-Quan Lu (a2)

Abstract

This paper describes a wireless-bond interconnect technique, termed Dimple-Array Interconnect (DAI) technique for packaging power devices. Electrical connections onto the devices are established by soldering arrays of dimples pre-formed on a metal sheet. Preliminary experimental and analytical results demonstrated potential advantages of this technique such as reduced parasitic noises, improved heat dissipation, as well as lowered processing complexity, compared to the conventional wire bonding technology in power module manufacturing. Thermomechanical analysis using thermal cycling test and FEM were also performed to evaluate the reliability characteristics of this interconnect technique for power devices.

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A Dimple-Array Interconnect Technique for Power Semiconductor Devices

  • Simon S. Wen (a1), Daniel Huff (a2) and Guo-Quan Lu (a2)

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