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Dielectric breakdown Characteristics of poly-Si/HfAlOx/SiON gate stack

  • Kazuyoshi Torii (a1), Hiroshi Ohji (a1), Akiyoshi Mutoh (a1), Takaaki Kawahara (a1), Riichiro Mitsuhashi (a1), Atsushi Horiuchi (a1), S. Miyazaki (a2) and Hiroshi Kitajima (a1)...

Abstract

The dielectric breakdown behavior of poly-Si gate CMOSFETs with HfAlOx/SiON gate dielectric fabricated using mass production worthy 300 mm process was investigated. If SiO2 is used as an interfacial layer (IL), the IL reduction and the intermixing between the HfAlOx layer and the IL occurred, which causes extrinsic breakdown. By using the SiON of [N]=18% as an IL and setting the maximum temperature after the HfAlOx deposition to be 1000°C, the interfacial reaction was suppressed and the extrinsic breakdown component was eliminated. In the case of the n-capacitor accumulation, an abrupt increase of gate leakage was observed, which is believed to correspond to the IL breakdown. The mean time to failure (MTTF for 0.1cm2 at 125°C) is long enough. On the other hand, gate current initially decreases and then starts to increase in the case of p-capacitor accumulation. If we define the time to breakdown at the onset of current increase, the MTTF would be only 3.7 years if it obeys the V-plot (MTTF predicted by 1/V-plot was 1.6×107 years).

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[1] Kauerauf, T., Degraeve, R., Cartier, E., et al. : Tech. Digest IEDM, p.521 (2002)
[2] Loh, W-Y, Cho, B-J, Joo, M-S, et al. : Tech. Digest IEDM, p.927 (2003)
[3] Mitsuhashi, R., Horiuchi, A., Uedono, A., et al. : Ext. Abst. International Workshop on Gate Insulator, p.150 (2003)
[4] Ohta, A., Miyazaki, S., Murakami, H. et al. , Abst. 7th Int. Conf. Atomically Controlled Surfaces and Nanostructures (2003) p.255
[5] Degreave, R., Groeseneken, G., Bellens, R. et al. , Trans. Electron Devices, 45, 904 (1999)

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