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Development of a Post-Spacer Etch Clean to Improve Silicide Formation

  • Edward K. Yeh (a1), Samit S. Sengupta (a1) and Calvin T. Gabriel (a1)


The formation of a uniform, low-resistance silicide is dependent on the contamination level of the silicon surface upon which the Ti or Co is deposited. Contamination may be in the form of embedded carbon and fluorine residues from previous processing steps, such as the LDD spacer etch. The extent to which the spacer etch contributes impurities can be determined by making contact angle measurements; that is, measurement of the angle formed by a droplet of water placed on the wafer surface. A clean silicon surface provides a contact angle of > 70°, whereas a contaminated silicon surface produces contact angles down to only a few degrees. By using contact angle as a metric, a post-spacer etch clean was developed to remove impurities from the silicon surface without significant silicon loss. The clean procedure entails the use of a CF4/H2O plasma to treat the wafer directly after spacer etch. The clean process was then evaluated by the formation of a blanket Ti silicide followed by sheet resistance measurement. By using this cleaning process, a Ti silicide sheet resistance comparable to that formed on virgin silicon wafers was obtained on wafers that experienced the spacer etch. By comparison, wafers that were subjected to the spacer etch but not the post-spacer clean yielded a higher sheet resistance. Additional study of the post-spacer etch clean process revealed that oxide on the wafer (even the small amount formed during an O2-based resist ash process) can prevent the CF4/H2O plasma from cleaning the surface, perhaps by blocking H in the cleaning plasma from extracting C and other contaminants from the silicon surface. Co silicide formation is even more sensitive to surface impurities than Ti silicide. Using the same post-spacer etch clean, uniform, low-resistance Co silicide formation has been demonstrated.



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1. Unpublished results of Lin, X.-W., Harvey, I., Lee, H., and Solis, R. while at VLSI Technology, Inc. See also U. S. Patent No. 5,895,245.
2. Solis, R., Harvey, I., and Gabriel, C., Proc. 6th Intl. Symp. on Semiconductor Manufacturing (1997).

Development of a Post-Spacer Etch Clean to Improve Silicide Formation

  • Edward K. Yeh (a1), Samit S. Sengupta (a1) and Calvin T. Gabriel (a1)


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