Skip to main content Accessibility help

Development of 3D-Packaging Process Technology for Stacked Memory Chips


A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.



Hide All
1. Takahashi, Kenji et al., “Process Integration of 3D Chip Stack with Vertical Interconnection” in Proc. 2004Electronic Components and Technology Conference, pp. 601609
2. Garrou, Philip, “3D Integration: A Status Report” in Proc. 3D Architectures for Semiconductor Integration and Packaging, Tempe, Arizona, June, 2005
3. Ikeda, H., Kawano, M. and Mitsuhashi, T., “Stacked Memory Chip Technology Development”, SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 3742.


Development of 3D-Packaging Process Technology for Stacked Memory Chips


Full text views

Total number of HTML views: 0
Total number of PDF views: 0 *
Loading metrics...

Abstract views

Total abstract views: 0 *
Loading metrics...

* Views captured on Cambridge Core between <date>. This data will be updated every 24 hours.

Usage data cannot currently be displayed