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Demonstration of Hybrid Silicon-on-Silicon Carbide Wafers and Electrical Test Structures with Improved Thermal Performance

  • Steven G. Whipple (a1), John T. Torvik (a2), Randolph E. Treece (a3) and Jeffrey T. Bernacki (a4)


Multiple 50 mm hybrid Si-on-SiC substrates consisting of thin film [100] Si (1 μm) on bulk semi-insulating [0001] 6H-SiC wafers were fabricated using low-temperature (150°C) wafer bonding and slicing techniques. A set of samples were prepared comparing various thicknesses of SiO2 (60, 120, 190, 240 and 520 nm) as an intermediate bonding layer between the two materials. A variety of test structures such as Van der Pauw structures, linear transfer-length measurement arrays and resistors were fabricated in the Si layers using standard Si processing (such as lithography, B-diffusion, etching and oxidation) in order to characterize the robustness as well as the electrical and thermal properties of the hybrid substrates. Bulk Si and Si-on-insulator (SOI) substrates were used for comparison. We report the Si layers on the hybrid Si-on-SiC substrates to be device-grade in terms of mobility and crystal structure, and that their device-to-device electrical isolation properties are superior to those of bulk Si and comparable to those of SOI. Furthermore, electrical test structures on hybrid Si-on-SiC substrates exhibit vastly superior heat dissipation compared to equivalent devices on bulk Si or SOI. Specifically, the temperature rise can be as much as 102°C lower in resistor devices made on Si-on-SiC (Tj= 191°C) compared to on bulk Si (Tj= 293C) under high-power density operation (67 kW/cm2). We also describe the effects of intermediate oxide thickness on thermal resistance.



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