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Backside Copper Contamination Issues in CMOS Process Integration – A Case Study

  • K. Prasad (a1), K.C. Tee (a1), L. Chan (a2) and A. K. See (a2)

Abstract

NMOS and PMOS transistors of various (W/L) ratios, down to 0.24µm channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. A thin layer of copper film was deposited on the back surface of the wafer. Over 10 hours of annealing at 4000C was carried out. Electrical parameters such as the threshold voltage (VT0), the drain saturation current (IDsat) and the off-current (Ioff), for transistors, and the leakage current for large diodes were measured. Secondary Ion Mass Spectroscopy (SIMS) was used to monitor the copper diffusion. Even after 10 hours of annealing at 400°C, electrical parameters of both NMOS and PMOS devices and leakage currents of diodes showed no significant degradation.

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Backside Copper Contamination Issues in CMOS Process Integration – A Case Study

  • K. Prasad (a1), K.C. Tee (a1), L. Chan (a2) and A. K. See (a2)

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