Hostname: page-component-76fb5796d-r6qrq Total loading time: 0 Render date: 2024-04-25T10:26:59.250Z Has data issue: false hasContentIssue false
  • English
  • Français

‘Back end’ Chemical Cleaning in integrated Circuit Fabrication: a Tutorial

Published online by Cambridge University Press:  10 February 2011

Yaw S. Obeng  and
R. S. Raghavan
Yaw S. Obeng
Affiliation:
Lucent Technologies Bell Laboratories 9333 South John Young Parkway, Orlando, F1 32819
R. S. Raghavan
Affiliation:
Lucent Technologies Bell Laboratories 700 Mountain Avenue, Murray Hill, NJ 07974
Get access

Abstract

The applications of wet chemical cleaning at the ‘back-end’ of Integrated Circuit (IC) or Metal-Oxide Semiconductor (MOS) fabrication are reviewed from chemical, environmental and cost perspectives. The various classes of commercially available “solvents” and “cryogenic” cleans are reviewed from the perspective of process suitability, impact on device yield and waste management. Strategies for minimizing processing concerns, as well as alternatives to organic solvent based wet chemical processing will also be discussed. Bulk photoresist (PR) stripping, post metal definition-, and post window etch cleaning are used to illustrate the discussion.

The use of radiotracing as a diagnostic tool in understanding the mechanism for metallic contamination during solvent cleans is also discussed. Data suggesting how the chemistry and solvent composition affects alkali metal (for example, sodium) contamination of dielectric- and barrier films during IC processing will also be presented.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 477 , 1997 , 145
Copyright
Copyright © Materials Research Society 1997

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 “Dielectric Materials for Advanced VLSI and ULSI Technologies”, Obeng, Y.S.; Steiner, K.G.; Velaga, A.N.; Pai, C.-S., AT&T Technical Journal, May/June 1994, 73 (3), 94–111 10.1002/j.1538-7305.1994.tb00591.xCrossRefGoogle Scholar
2 “Handbook of Semiconductor Wafer Cleaning Technology: Science, Technology, and Application”, Kern, W., , W., ed, Noyce Press, Park Ridge, New Jersey, 1993 Google Scholar
3 Lorenz, W.J.; Mansfield, F. “A New Classification Concept of Corrosion Inhibition - Model Investigations of Microstructured Electrodes” in ‘H. H. Uhlig Memorial Symposium’, Corrosion Monograph Series, Proceedings Volume 94–26, Mansfiled, F. et al, eds., The Electrochemical Society, 1995, pp. 176–191Google Scholar
4 “Thin Film Pitting: Is NMP the Culprit?”, Lee, F.T.; Wanlass, D. R.; Walsh, B., Semiconductor International, June 1994, pp. 175–180Google Scholar
5 ‘A Proven Sub-Micron Photoresist Stripper Solution for Post Metal and Via Hole Processes’, Lee, W. M., EKC Technologies, Inc. technical bulletin, 1993 Google Scholar
6 Fine, S. A., ACSI, In., Milpitas, CA., Private CommunicationGoogle Scholar
8 Table 6–1, ‘Lange's handbook of Chemistry’, 13th Ed., Dean, J. A., ed, McGraw-Hill Book Company, New York, 1985 Google Scholar
9 ‘Comprehensive Inorganic Chemistry’, Bailar, J. C.; Emeleus, H. J.; Nyholm, R.; Trotman-Dickenson, A. F., eds., Pergamon Press, London, 1973, pp 272–273 Google Scholar
10 ‘Interferometry Based Real Time Resist Strip Monitoring’, Porfiris, N., presented at the “Wafer Cleaning Technology Symposium”, sponsored by EKC Technologies, Inc., July 29, 1994, Mascone Center, San Francisco.Google Scholar
11 ‘Pr iming of Silicon Substrates with Trimethylsilyl Containg Compounds’, Michielson, M.C.B.A.; Morrit, V.B.; Ponjee, J.J.; Touwslager, F.J.; Moonen, J.A.H.M, Microelectronic Engineering 11, 1990, 475–480 Google Scholar
12 Takahashi, K.M.; Sapjeta, B.J.; Hanson, K. J., “Controlled Etching of Titanium Films used as Glue Layers Beneath Copper Conductors”, Presented at the Electrochemical Society Fall Meeting, Orlando, Fl., October 9–14, 1994Google Scholar
13 ‘CE Series: Controlled Oxide Etch and SWP Removal’, Ashland-ACT, Allentown, PA, Technical BulletinGoogle Scholar
14 Colonnel, J. et al. Unpublished DataGoogle Scholar
15 “Applications of NOE Etch in Selective Removal of Silicon Dioxide Residues and High Porosity Oxide Surface Layers', Fine, S.A.; Koffenstein, T.; Switalski, D.; Bowen, B., ACSI, Inc., Milpitas, CA Technical BulletinGoogle Scholar
16 Obeng, Y. S., US Patent # 5417802, Issued on 5/23/95Google Scholar
17 (a) Soriano, L. et al. , J. Vac. Sci. Technol. 11 (47)1993; (b) N. C. Saha and H. G Tompkins J. AppI Phys. 72 (3072) 1992CrossRefGoogle Scholar
18 (a) ‘Legacy Systems, Inc. Coldstrip’, Brautigam, L; Muti, C.; Matthews, R. private communication, (b) ‘‘Acid-Free Process Removes Photoresist’, Dax, M., Semiconductor International, October 1996, p. 74 Google Scholar
19 ‘Carbon Dioxide Cleaning’, Cline, C. M., Precision Cleaning Magazine, December 1996, p. 30Google Scholar
20 ‘FSI ARIES Process Review: Presentation to Sematech S79 Project Committee’, Butterbaugh, J.; Barnett, J., August 27, 1996 Google Scholar