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Analysis of Nanotopography in Silicon Generated by the Polishing Process

Published online by Cambridge University Press:  15 March 2011

Hiromichi Isogai  and
Katsuyoshi Kojima
Hiromichi Isogai
Affiliation:
TOSHIBA CERAMICS CO., LTD., Silicon Company, Wafer Processing Technology 6-861-5 Higashikou Seiroumachi Kitakanbaragun Niigata Prefecture, Japan
Katsuyoshi Kojima
Affiliation:
TOSHIBA CERAMICS CO., LTD., Silicon Company, Wafer Processing Technology 6-861-5 Higashikou Seiroumachi Kitakanbaragun Niigata Prefecture, Japan
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Abstract

This paper describes a new model, which analyzes the effects of the polishing conditions on nanotopography after polishing silicon (Si) substrates. The thickness uniformity of dielectric oxide-films after Chemical Mechanical Polishing (CMP) is affected by nanotopography of the Si substrate. Therefore, reducing nanotopography in Si substrates is essential in order to obtain highly uniform dielectric film thickness after CMP. We have developed a model based on Preston's equation for estimating the change in nanotopography of Si substrates due to polishing. In this model, various conditions relating to the structure of the polishing apparatus, the polishing pad material and the motion of the substrate can be taken into consideration. To investigate the influence of the polishing conditions on nanotopography, we compared experimental polishing results with calculations using this model. Thus, it was clarified that the generation of nanotopography in the polishing process that determines the final shape of the substrate, depends on the history of the pressure and contact distance produced during the process.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 816: Symposium K – Advances in Chemical-Mechanical Polishing , 2004 , K7.3
Copyright
Copyright © Materials Research Society 2004

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