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Analysis of Drain Currents During Switching off a-Si:H Based Thin Film Transistors

  • F. Lemmi (a1) and R. A. Street (a1)


We present measurements and analysis of a-Si:H thin film transistor (TFT) transients when the gate voltage switches the device from a conducting to a non-conducting state. The drain current transient has been monitored in the medium-long (Ims-100s) time range and exhibits a power law decay extending to at least 10 seconds. The decay has been studied over a range of drain voltages and gate off-state voltages. Measured data show that the gate off-state can help to obtain a low drain leakage current at long times when high drain voltages are being used.

However, the decay at low drain voltages shows little sensitivity to different gate off-state voltages. An analytical model is developed, based on the relaxation of the Fermi level toward mid-gap in a spatially uniform TFT channel. The model shows how deep defects are responsible for the current decay slope at long times, while shallower states determine the slope in the short time range. An energy-independent defect density would produce a 1/t slope for the current decay. Shallow states and deep states affect in opposite ways the slope since their density is energydependent in opposite ways as Fermi level moves deeper into the band-gap. Furthermore, long decay times are associated with a wider depletion region in the channel and increase the total number of defect states involved. A steeper decay than 1/t is expected and observed for shorttime ranges, while a more gradual (about 1/t 1/2) one corresponds to long time measurements. The implications of the transient decay for the performance of active matrix arrays will be discussed.



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