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Amorphous Silicon Vertical Thin Film Transistor for High Density Integration

Published online by Cambridge University Press:  01 February 2011

Isaac Chan  and
Arokia Nathan
Isaac Chan
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
Arokia Nathan
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada
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Abstract

This paper presents a fabrication process for vertical thin film transistors (VTFT) based on hydrogenated amorphous silicon (a-Si:H) technology. This process yields VTFTs with an ON/OFF ratio of 105 and a leakage current of the order of 10-13A for a channel length of 1 μm. The device structure, because of significant undercutting formed after dry-etch process (reactive ion etching or RIE), has a channel profile that is skewed as opposed to vertical. This serves to compromise the structural integrity and the electrical performance of the device. Therefore, an anisotropic dry-etch process for this channel profile is being developed. It is found that a CF4/20%H2 gas mixture yields a sharp vertical sidewall profile. In addition, a modified masking process has been developed to produce a rectangular photoresist profile so as to achieve an anisotropic etch profile for the channel region. The effects of the photoresist geometry on the anisotropic dry-etch process will be discussed.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 715: Symposium A – Amorphous and Heterogeneous Silicon-Based Films-2002 , 2002 , A12.6
Copyright
Copyright © Materials Research Society 2002

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