Published online by Cambridge University Press: 21 February 2011
In this paper we present both experimental data and computer simulations of the leakage characteristics of amorphous silicon (a-Si) thin film transistors operated under time transient conditions. The transient behaviour of these devices for realistic operating conditions is often very different from their steady-state characteristics, due to the slow response of deep traps in a-Si. Our model is in good agreement with the data and realistically accounts for the time-dependent behaviour of amorphous silicon with leakage being mainly determined by a combination of fixed charge in the passivation dielectric and a distribution of surface states at the top silicon interface. We show how voltage pulses applied to the gate of a TFT affect its performance as a pixel switch in a two-dimensional array. In particular we concentrate on the effects of light and bias stressing.
Full text views reflects PDF downloads, PDFs sent to Google Drive, Dropbox and Kindle and HTML full text views.
* Views captured on Cambridge Core between September 2016 - 28th January 2021. This data will be updated every 24 hours.