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Study of Electrical Properties of Defects in Soi Films by Wafer Bonding

Published online by Cambridge University Press:  03 September 2012

Akira Usami
Nagoya Institute of Technology, Nagoya 466, Japan
Taichi Natori
Nagoya Institute of Technology, Nagoya 466, Japan
Akira Ito
Nagoya Institute of Technology, Nagoya 466, Japan
Shun-ichiro Ishigami
Mitsubishi Material Co., Ltd., Omiya 330, Japan
Yutaka Tokuda
Aichi Institute of Technology, Yakusa, Toyota 470–03, Japan.
Takao Wada
Nagoya Institute of Technology, Nagoya 466, Japan
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Silicon-on-insulator films fabricated by the wafer bonding technique were studied with capacitance-voltage (c-V) and deep-level transient spectroscopy (DLTS) measurements. For our experiments, two kinds of SOI wafers were prepared. Many voids were present in one sample (void sample), but few voids were in the other sample (no void sample). Before annealing, two DLTS peaks (E-0.48 eV and Ec-0.38 eV) were observed in the SOI layer of the void sample. For the no void sample, different two DLTS peaks (Ec-0.16 eV and Ec-0.12 eV) were observed. The trap with an activation energy of 0.48 eV was annealed out after 450 °C annealing for 24 h. On the other hand, other traps were annealed out after 450 °C annealing for several hours. During annealing at 450 °C, thermal donors (TDs) were formed simultaneously. In usual CZ sil icon, a DLTS peak of TD was observed around 60 K. In the no void sample, however, a TD peak was observed at a temperature lower than 30 K. This TD was annihilated by rapid thermal annealing. This suggests that the TD with a shallower level was formed in the no void sample after annealing at 450 °C.

Research Article
Copyright © Materials Research Society 1992

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