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Staggered CMOS: A Novel Three-Dimensional Technology

Published online by Cambridge University Press:  21 February 2011

E. W. Maby
Affiliation:
Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology, Cambridge, MA 02139
D. A. Antoniadis
Affiliation:
Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology, Cambridge, MA 02139
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Abstract

We report the fabrication of mutually self-aligned IGFET's in two silicon layers which are separated by a thin dielectric film. The transistors are configured such that the heavily doped source and drain regions of a transistor in one layer also serve as the gate electrodes for transistors in the other layer. One application of this three-dimensional technology is the implementation of a compact four-transistor “staggered” CMOS latch circuit which can be used to form part of a static random-access memory cell.

Type
Research Article
Copyright
Copyright © Materials Research Society 1984

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References

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