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A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

Published online by Cambridge University Press:  01 February 2011

John Sudijono
Affiliation:
sudijono@us.ibm.com, Chartered Semiconductor, Hopewell Junction, NY, 12533, United States
Alok Jain
Affiliation:
alok_jain@amat.com, Applied Materials, Santa Clara, CA, 95054, United States
Shankar Venkataraman
Affiliation:
Shankar_Venkataraman@amat.com, Applied Materials, Santa Clara, CA, 95054, United States
Sunder Thirupapuliyur
Affiliation:
Sunderraj_Thirupapuliyur@amat.com, Applied Materials, Santa Clara, CA, 95054, United States
Harry Whitesell
Affiliation:
Harry_whitesell@amat.com, Applied Materials, Santa Clara, CA, 95054, United States
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Abstract

This work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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