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Improvement of Gate Oxide Integrity in Low Temperature Poly Silicon TFT

Published online by Cambridge University Press:  01 February 2011

Seok-Woo Lee
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
Dae Hyun Nam
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
Jin Mo Yoon
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
Hyun Sik Seo
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
Kyoung Moon Lim
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
Chang-Dong Kim
Affiliation:
LCD R&D Center, LG.Philips LCD, 533, Hogae-dong, Dongan-gu, Anyang-si, Kyongki-do, 431-080, Korea
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Abstract

The electrical characteristics of SiH4-based PECVD gate oxide have been investigated with respect to gate oxide integrity (GOI) and its reliability. It was found that the GOI of poly-Si TFT integrated on glass substrate strongly depended on the charge trapping and deep level interface states generation under Fowler-Nordheim stress (FNS). By applying elevated temperature postanneal without vacuum break after the gate oxide deposition, highly reliable gate oxide was obtained. Under FNS, ID-VG curve showed severe shift and degradation of subthreshold slope, which were reduced by adopting post-annealed gate oxide. Besides, the TFT with post-annealed gate oxide showed around 10 times higher charge to breakdown than that of as-deposited gate oxide. Charge to breakdown of MOS capacitors were also studied. By applying post-annealed gate oxide, charge to breakdown drastically improved, which could be explained by reduced charge trapping under FNS.

Type
Research Article
Copyright
Copyright © Materials Research Society 2003

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References

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