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FEM Analysis of Thermal Stresses in Advanced Electronic Packages

Published online by Cambridge University Press:  10 February 2011

Sven Rzepka
Affiliation:
Dept. of Electrical Engineering, Dresden University of Technology, D-01062 Dresden, Germany
Matt A. Korhonen
Affiliation:
Dept. of Materials Science and Engineering, Cornell University, Ithaca, NY 15853-1501, USA
Che-Yu Li
Affiliation:
Dept. of Materials Science and Engineering, Cornell University, Ithaca, NY 15853-1501, USA
Ekkehard Meusel
Affiliation:
Dept. of Electrical Engineering, Dresden University of Technology, D-01062 Dresden, Germany
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Abstract

Following the general tendency of downsizing in microelectronic packages, the interposing layer between silicon chip and organic board is constantly reduced while the differences in thermal expansion stay constant. Consequently, thermal stresses have become the most important reliability concern in advanced packages. Finite element analysis is known as an effective way of theoretically studying the mechanical situation in multi-component systems with complex material behavior. The paper presents results of finite element simulations that provide practical guidance for design, process and material developments of chip size packaging (CSP), flip chip (FC), and direct chip attach (DCA) modules. Using realistic and efficient models, a low-cost CSP concept is assessed, the effects of underfill, underfill imperfections, and underfill defects on the reliability of FC modules are studied, and an optimum set of mechanical properties for underfill materials is proposed. Finally, reliability risk factors in DCA modules are identified and preliminary design guidelines are given.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

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