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Direct Growth of III-V Devices on Silicon

Published online by Cambridge University Press:  01 February 2011

Katherine Herrick
Affiliation:
kherrick@raytheon.com, Raytheon Tewksbury, Advanced Technology, Tewksbury, MA, 01876, United States
Thomas Kazior
Affiliation:
Thomas_E_Kazior@raytheon.com, Raytheon RF Components, Advanced Technology, Andover, MA, 01810, United States
Amy Liu
Affiliation:
aliu@iqep.com, IQE Inc., Bethlehem, PA, 08873, United States
Dmitri I. Loubychev
Affiliation:
Dmitri@iqep.com, IQE Inc., Bethlehem, PA, 08873, United States
Joel M. Fastenau
Affiliation:
jfastenau@iqep.com, IQE Inc., Bethlehem, PA, 08873, United States
Miguel Urteaga
Affiliation:
murteaga@teledyne.com, Teledyne Scientific Company, Thousand Oaks, CA, 91360, United States
Eugene A. Fitzgerald
Affiliation:
eafitz@mit.edu, Massachusetts Institute of Technology, Department of Materials Science and Engineering, Cambridge, MA, 02139, United States
Mayank T. Bulsara
Affiliation:
mbulsara@mit.edu, Massachusetts Institute of Technology, Department of Materials Science and Engineering, Cambridge, MA, 02139, United States
David Clark
Affiliation:
david.clark@raytheon.co.uk, Raytheon Systems Limited, Glenrothes, Scotland, N/A, United Kingdom
Berinder Brar
Affiliation:
bbrar@teledyne.com, Teledyne Scientific Company, Thousand Oaks, CA, 91360, United States
Wonill Ha
Affiliation:
wha@teledyne.com, Teledyne Scientific Company, Thousand Oaks, CA, 91360, United States
Joshua Bergman
Affiliation:
jbergman@teledyne.com, Teledyne Scientific Company, Thousand Oaks, CA, 91360, United States
Nicolas Daval
Affiliation:
nicolas.daval@soitec.fr, SOITEC, Bernin, N/A, France
Jeffrey LaRoche
Affiliation:
jeffrey_laroche@raytheon.com, Raytheon RF Components, Advanced Technology, Andover, MA, 01810, United States
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Abstract

Our direct growth approach of integrating compound semiconductors (CS) and silicon CMOS is based on a unique silicon template wafer with an embedded CS template layer of Germanium (Ge). It enables selective placement of CS devices in arbitrary locations on a Silicon CMOS wafer for simple, high yield, monolithic integration and optimal circuit performance. HBTs demonstrate a peak current gain cutoff frequency ft of 170GHz at a nominal collector current density of 2mA/μm2. To the best of our knowledge this represents the first demonstration of an InP-based HBT fabricated on a silicon wafer.

Type
Research Article
Copyright
Copyright © Materials Research Society 2008

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References

1. Mazuré, Carlos and Celler, George K.. “Advanced Electronic Substrates for the Nanotechnology Era.”, The Electrochemical Society Interface, Winter (2006-2007).Google Scholar
2. Deguet, C., Sanchez, L., Akatsu, T., Allibert, F., Dechamp, J., Madeira, F., Mazen, F., Tauzin, A., Loup, V., Richtarch, C., Mercier, D., Signamarcheix, T., Letertre, F., Depuydt, B., and Kernevez, N.. “Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium.” Electronics Letters 42 (7) 30 March (2006): 415417.CrossRefGoogle Scholar
3. Maleville, C. and Mazure, C.. “Smart CutTM technology: From 300 mm ultrathin SOI production to advanced engineered substrates.” Solid-State Electron. 48 (6) June (2004). 10551063.CrossRefGoogle Scholar
4.Molecular-beam epitaxy production of large-diameter metamorphic high electron mobility transistor and heterojunction bipolar transistor wafers, by Baklenov, O., Lubyshev, D., Wu, Y., Fang, X.-M., Fastenau, J.M., Leung, L., Towner, F.J., Cornfeld, A.B., and Liu, W.K., published May/June 2002 Google Scholar
5.Monolithic CMOS-compatible AlGaInP visible LED arrays on Silicon on Lattice-Engineered Substrates (SOLES), by Chilukuri, Kamesh, Mori, Michael J., Dohrmanand, Carl L., Fitzgerald, Eugene A., published November 2006 Google Scholar

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