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Detailed Investigation of GaN Metal-Insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods

Published online by Cambridge University Press:  01 February 2011

Junjiroh Kikawa
Affiliation:, Ritaumeikan University, Kusatsu, Japan
Yuki Horiuchi
Affiliation:, Ritsumeikan University, Kusatsu, Japan
Eiji Shibata
Affiliation:, Ritsumeikan University, Kusatsu, Japan
Masamitsu Kaneko
Affiliation:, Ritsumeikan University, Kusatsu, Japan
Hirotaka Otake
Affiliation:, ROHM Co.,Ltd., Kyoto, Japan
Tatsuya Fujishima
Affiliation:, ROHM Co.,Ltd., Kyoto, Japan
Kentaro Chikamatsu
Affiliation:, ROHM Co.,Ltd., Kyoto, Japan
Atsushi Yamaguchi
Affiliation:, ROHM Co.,Ltd., Kyoto, Japan
Yasushi Nanishi
Affiliation:, Ritsumeikan University, Kusatsu, Japan
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Interface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail.Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min.CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency.

In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window.

Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).

Research Article
Copyright © Materials Research Society 2009

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