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Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics

Published online by Cambridge University Press:  10 February 2011

Yider Wu
Affiliation:
Departments of Electrical and Computer Engineering, and Physics, North Carolina State University, Raleigh, NC 27695-8202, USA
Gerald Lucovsky
Affiliation:
Departments of Electrical and Computer Engineering, and Physics, North Carolina State University, Raleigh, NC 27695-8202, USA
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Abstract

Ultrathin (tox,eq < 2.0 nm) Si3N4/SiO2(hereafter N/O) gate dielectrics with improved interface characteristics compared to devices with thermal oxides have been formed by remote plasma enhanced CVD of Si3N4onto oxides. If the Si-Si02 interface is intentionally nitrided prior to the Si3N4deposition, the increased physical thickness of the N/O stack combined with the interfacial nitridation reduces the direct tunneling current by more than two orders of magnitude. The ensuing device structure can then be characterized as N/O/N. The top nitride layer is also an effective boron diffusion barrier improving short channel characteristics in p+-poly PMOSFETs. In addition, nitrogen can also be transported to the silicon/dielectric interface during post-deposition RTAs, and this reduces degradation of transconductance during hot carrier stressing.

Type
Research Article
Copyright
Copyright © Materials Research Society 1999

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Aggressively Scaled P-Channel Mosfets With Stacked Nitride-Oxide-Nitride, N/O/N, Gate Dielectrics
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