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32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Alloy Seed

  • Shaoning Yao (a1), Vincent McGahay (a1), Matthew S. Angyal (a1), Andrew H. Simon (a1), Tom C. Lee (a2), Cathryn Christiansen (a2), Baozhen Li (a2), Fen Chen (a2), Paul S. McLaughlin (a1), Oluwafemi O. Ogunsola (a1) and Stephan Grunow (a1)...

Abstract

This paper introduces a highly reliable Cu interconnect technology at the 32 nm node with CuMn alloy seed. A CuMn alloy liner seed process combined with a non-gouging liner has been integrated into the minimum-pitch wiring level. Stress migration fails with CuMn seed at plate-below-via structures were shut down by a non-gouging liner process. Integration with gouging liner and non-gouging liner is compared, and results of interaction with CuMn seed are discussed in this paper.

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1. Christiansen, C., et al. ., “Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects”, IEEE Inter. Rel. Phys. Symp (IRPS) 2011.
2. Nogami, T., et al. ., “High reliability 32nm Cu/ULK BEOL based on PVD CuMn seed and its extendibility”, IEDM 2010, 33.5.133.5.
3. Edelstein, D., et al. ., “Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low- k BEOL,” in Proc. IEEE Int. Rel. Phys. Symp., 2004, pp. 316319.
4. Clevenger, L., et al. ., “Reliability challenges in copper metallizations arising with the PVD resputter liner engineering for 65 nmand beyond,” in Proc. IEEE Int. Rel. Phys. Symp., 2007, pp. 511515.
5. Yang, C.-C., et al. ., “Enhanced Via Integration Process for Copper/Ultralow-k Interconnects”, IEEE Electron Device Letters, Vol. 31, No. 4, 2010.

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