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Evaluation of novel carrier substrates for high reliability and integrated GaN devices in a 200 mm complementary metal–oxide semiconductor compatible process

Published online by Cambridge University Press:  17 September 2018

S. Stoffels ,
K. Geens ,
X. Li ,
D. Wellekens ,
S. You ,
M. Zhao ,
M. Borga ,
E. Zanoni ,
G. Meneghesso  and
M. Meneghini
...Show all authors
S. Stoffels*
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
K. Geens
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
X. Li
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
D. Wellekens
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
S. You
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
M. Zhao
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
M. Borga
Affiliation:
Dipartimento di Ingegneria dell'Informazione, University degli studi di Padova, Padova, Italy
E. Zanoni
Affiliation:
Dipartimento di Ingegneria dell'Informazione, University degli studi di Padova, Padova, Italy
G. Meneghesso
Affiliation:
Dipartimento di Ingegneria dell'Informazione, University degli studi di Padova, Padova, Italy
M. Meneghini
Affiliation:
Dipartimento di Ingegneria dell'Informazione, University degli studi di Padova, Padova, Italy
N.E. Posthuma
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
M. Van Hove
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
S. Decoutere
Affiliation:
PMST, IMEC, Kapeldreef 75, Heverlee, Vlaams-Brabant, Belgium
*
Address all correspondence to S. Stoffels at steve.stoffels@imec.be
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Abstract

In this paper new materials and substrate approaches are discussed which have potential to provide (Al)GaN buffers with a better crystal quality, higher critical electrical field, or thickness and have the potential to offer co-integration of GaN switches at different reference potentials, while maintaining lower wafer bow and maintaining complementary metal–oxide semiconductor (CMOS) compatibility. Engineered silicon substrates, silicon on insulator (SOI) and coefficient of thermal expansion (CTE)-matched substrates have been investigated and benchmarked with respect to each other. SOI and CTE-matched offer benefits for scaling to higher voltage, while a trench isolation process combined with an oxide interlayer substrate allows co-integration of GaN components in a GaN-integrated circuit (IC).

Type
Research Letters
Information
MRS Communications , Volume 8 , Issue 4 , December 2018 , pp. 1387 - 1394
Copyright
Copyright © Materials Research Society 2018 

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