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Scaling Transistors into the Deep-Submicron Regime

Published online by Cambridge University Press:  31 January 2011

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The dominant device used in the semiconductor industry today is the silicon-based metal oxide semiconductor (MOS) transistor. The MOS transistor consists of a source, drain, channel, and gate region fabricated in single-crystal silicon (Figure 1). The source region provides a supply of mobile charge when the device is turned “on.” The source is electrically isolated from the drain by the channel region, which is oppositely charged. An insulating oxide layer between the gate and the channel region forms a capacitor. During operation, a voltage is applied to the gate. By applying the appropriate voltage, a conductive layer of charge can be attracted in the channel region at the oxide/silicon interface. This layer of charge acts as a wire that effectively connects the source and drain regions. By changing the voltage on the gate, the conducting layer of charge can be removed. Thus the transistor acts like a switch, with the gate electrode controlling the connection from the source to the drain. These individual switches can be connected to form the basic building blocks for circuit design. These building blocks are used to create the high-performance microprocessors and memory chips in today's computers.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

1.Dennard, R.H., Gaensslen, F.H., Yu, H.N., Rideout, V.L., Bassous, E., and LeBlanc, A.R., IEEE J. Solid-State Circuits 9 (5) (1974) p. 256.CrossRefGoogle Scholar
2.The International Technology Roadmap for Semiconductors, 1999 ed. (Semiconductor Industry Association, San Jose, CA, 1999).Google Scholar
3.Thompson, S.E., Packan, P.A., and Bohr, M.T., VLSI Tech. Dig. (1996) p. 154.Google Scholar
4.Lee, K.F., Yan, R.H., Jeon, D.Y., Chin, G.M., Kim, Y.O., Tennant, D.M., Razavi, B., Lin, H.D., Wey, Y.G., Westerwick, E.H., Morris, M.D., Johnson, R.W., Liu, T.M., Tarsia, M., Cerullo, M., Swartz, R.G., and Ourmazd, A., IEDM Tech. Dig. (1993) p. 131.Google Scholar
5.Jacobs, J.B. and Antoniadis, D., IEEE Trans. Electron. Devices (1995) p. 870.CrossRefGoogle Scholar
6.Taur, Y. and Nowak, E.J., IEDM Tech. Dig. (1997) p. 215.Google Scholar
7.Ponomarev, Y.V., Stolk, P.A., van Brandenburg, A.C.M.C., Dachs, C.J.J., Kaiser, M., Montree, A.H., Roes, R., Schmitz, J., and Woerlee, P.H., VLSI Tech. Dig. (1999) p. 65.Google Scholar