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Improvement in Uniformity of Type-II p-GaAsSb/n-InAs Nanowires on GaAs Substrates by the Insertion of GaAs Segments in Position-controlled VLS Method

Published online by Cambridge University Press:  06 February 2019

Kenichi Kawaguchi*
Affiliation:
Fujitsu Limited and Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
Tsuyoshi Takahashi
Affiliation:
Fujitsu Limited and Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
Naoya Okamoto
Affiliation:
Fujitsu Limited and Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
Masaru Sato
Affiliation:
Fujitsu Limited and Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan
Michihiko Suhara
Affiliation:
Tokyo Metropolitan University, 1-1 Minami-Osawa, Hachioji 192-0397, Japan
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Abstract

To improve the uniformity of type-II GaAsSb/InAs nanowires (NWs) grown on GaAs substrate using the position-controlled vapor-liquid-solid (VLS) method, the insertion of GaAs NW segments was investigated. In conventional InAs NWs grown directly on patterned GaAs substrate at 430°C, anomalous growth occurred in some pattern holes, and the proportion of holes having anomalous growth was in particular pronounced when a large Au catalyst diameter (80 nm) was employed, which indicates that the strain coming from the lattice-mismatched system affected the NW growth. With the insertion of GaAs segments, the yield of vertical NWs drastically improved for all pattern conditions. The uniformity of NWs was maintained after the growth of p-GaAsSb segments, and well-organized, two-dimensional arrays of type-II GaAsSb/InAs diode NWs were obtained. Moreover, the formation of p-n junctions at the GaAsSb/InAs interface was clearly observed using scanning capacitive microscopy. These results show that the investigated growth strategy is promising for the development of high-performance NW tunnel diodes.

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Articles
Copyright
Copyright © Materials Research Society 2019 

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References

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